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# Include br> ENTRY (_start)
ENTRY (ResetEntryPoint)
@
@ Exception vector table (physical address = 0x00000000)
@
@ 0x00 : Reset
b Reset
@ 0x04: Undefined instruction exception
UndefEntryPoint:
b HandleUndef
@ 0x08: Software disturb exception
SWIEntryPoint:
b HandleSWI
@ 0x0c: Prefetch Abort (Instruction Fetch Memory Abort)
PrefetchAbortEnteryPoint:
; b HandlePrefetchAbort
@ 0x10: Data Access Memory Abort
DataAbortEntryPoint:
b HandleDataAbort
@ 0x14: Not used
NotUsedEntryPoint:
b HandleNotUsed
@ 0x18: IRQ (Interrupt Request) exception
IRQEntryPoint:
b HandleIRQ
@ 0x1c: FIQ (Fast Interrupt Request) exception
FIQEntryPoint:
b HandleFIQ
@
@ VIVI magics
@
@ 0x20 : wizardry digit so we can verify that we merely put
. long 0
@ 0x24:
. long 0
@ 0x28: where this vivi was interlocked, so we can put it in memory in the right place
. long _start
@ 0x2C: this contains the platform, cpu and machine id
. long ARCHITECTURE_MAGIC
@ 0x30: vivi capabilities ;
. long 0
# ifdef CONFIG_PM
@ 0x34:
b SleepRamProc
# endif
# ifdef CONFIG_TEST
@ ; 0x38:
b hmi
# endif
@
@ Start VIVI head
@
Reset:
@ disable see dog clock
mov r1, # 0x53000000
mov r2, # 0x0
str r2, [r1]
@ maim all interrupts
mov r1, # INT_CTL_BASE
mov r2,tory burch bags Grand rite Grand ceremony, # 0xffffffff
str r2, [r1, # oINTMSK]
ldr r2, = 0x7ff
str r2, [r1, # oINTSUBMSK]
/ * @ initialise system ; clocks
mov r1, # CLK_CTL_BASE
mvn r2, # 0xff000000
str r2, [r1, # oLOCKTIME]
@ ldr r2, mpll_50mhz
@ str r2, [r1, # oMPLLCON]
* /

# define MDIV_405 0x7f . ascii STR_PREFETCH_ABORT:
. ascii
STR_FIQ:
. ascii >. ascii :
. ascii
# endif
. align 4
SerBase:
# whether defined (CONFIG_SERIAL_UART0)
. long UART0_CTL_BASE
# elif defined (CONFIG_SERIAL_UART1)
;. long UART1_CTL_BASE
# elif defined (CONFIG_SERIAL_UART2)
. long UART2_CTL_BASE
# else
# error no defined base address of reg code
# endif
# ifdef CONFIG_PM
. align 4
PMCTL0_ADDR:
. long 0x4c00000c
PMCTL1_ADDR:
. long 0x56000080
PMST_ADDR:
. long 0x560000B4
PMSR0_ADDR:
. long 0x560000B8
REFR_ADDR:
. long 0x48000024
# endif